[hpsdr] FW: OZY FPGA Configuration

[Bill Tracey]

I've programmed the ROM on Ozy via a ByteBlaster II clone without 
problem. When I've done this it was with no software loaded into the 
FX2 (in its default power on state) so perhaps hat's how we've 
avoided the output driving output issue?   I've not given it a lot of 
thought -- just know it has worked for me.

Regards,

Bill (kd5tfd)



At 11:30 AM 8/14/2008, Gerd Loch wrote:
>***** High Performance Software Defined Radio Discussion List *****
>
>may I repeat my question?
>
>-----Original Message-----
>From: Gerd Loch [mailto:g.loch at nt-electronics.de]
>Sent: Tuesday, July 15, 2008 2:06 PM
>To: 'hpsdr at hpsdr.org'
>Subject: OZY FPGA Configuration
>
>
>On Ozy the Cyclone II FPGA is being configured by the FX2 chip (Pins 72-77).
>
>The signals are:
>
>FPGA_DATA0          FX2 Pin72
>FPGA_NCONFIG        FX2 Pin73
>FPGA_DCLK           FX2 Pin74
>FPGA_CONFIG_DONE    FX2 Pin75
>FPGA_NSTATUS        FX2 Pin76
>FPGA_NCE            FX2 Pin77
>
>There is also a different way to configure the FPGA, the active serial mode.
>For this mode the Flash U1 must be programmed by an external programmer
>(Byteblaster II) which can be connected through HDR1.
>
>This progammer uses partly the same signals described above.
>
>For example the signal FPGA_DCLK is an output on FX2, but it is also an
>output on the Bytblaster II
>(Pin 1 HDR1) which results in output against output.
>
>Would it be a risk to connect the Byteblaster II or am I missing something?
>
>Gerd, DJ8AY



 1218777234.0