[hpsdr] Phoenix onboard 1GHz clock and project status

[Richard Hosking]

Thanks Andrew
We were planning to use the internal DDS PLL to multiply the 125MHz 
clock as the reference.
There may well be errors in the design  - it is only my eyes so far.
Kits of parts are still being collected - shouldnt be to long before an 
alpha board.
I was at Phil Harman';s house tonight - proof of concept for the Cyclops 
spectrum analyser is getting there - front end  as far as the 96MHz IF 
seems to work.
 
Richard
VK6BRO

Andrew wrote:
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> Hi All,
> Been looking at the Phoenix schematics and in particular the 1GHz clock.
> Looks like a very good board and I'm looking forward to seeing some 
> alpha results.
> However I'm a bit confused by the DDS clocking arrangement.
> There is a discrete crystal oscillator at 125MHz but the schematic 
> sheet is labelled 1GHz clock.
> One would therefore assume that the 8th harmonic from the mmic buffer 
> will be used to clock the DDS, if this is the case then there looks to 
> be a lot of filtering missing which would be needed to suppress the 
> lower harmonics??
> Am I missing something??? maybe someone could enlighten me?
>
> Many thanks,
> Andrew
>
> Bye the way, how is the project going, have boards been built yet?
> Any ideas about final populated board costs and target dates?
>
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