[hpsdr] Cascading ADC/FPGA Pairs

[L. Van Warren]

Graham -

What is the:
	- clock rate on an Alterra Cyclone?
	- sample rate of the fastest 16 bit ADC?
	- highest frequency one would want to process?

Van / AE5CC / wdv.com


-----Original Message-----
From: Graham / KE9H [mailto:KE9H at austin.rr.com] 
Sent: Thursday, August 20, 2009 10:43 AM
To: L. Van Warren
Cc: fallingstar at cauhf.org; hpsdr at openhpsdr.org
Subject: Re: [hpsdr] Cascading ADC/FPGA Pairs

L.Van:

That is the beauty of using the FPGA.  For dedicated logic tasks
like playing "put and take" with the output of several A->Ds, the
FPGA is faster than a CPU, particularly one subject to continuous
interruptions such as when a modern OS is involved.  The FPGA
can do multiple things in parallel, as opposed to the one thing at
a time, in series, that is characteristic of a CPU.  Note that the
FPGA the oscilloscope company used is the same Cyclone-III
family as HPSDR uses on Mercury.

--- Graham

 


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