[hpsdr] Cascading ADC/FPGA Pairs

[Graham / KE9H]

Van:

If we use the speed of the internal clock-tree distribution system
as the answer for your first question, the answer is 400 MHz for
the 'slow' parts we use in Mercury.

The sample rate for the fastest ("affordable", commercial, off the shelf)
16 bit A->D converter is less than 200 MHz. (160 or 180 MHz.)

A one GHz total effective sample rate would allow a receiver
that looked at 0 to 470 Mhz simultaneously.

So managing five A-D's running in parallel, on shifted phase clocks at
200 MHz sample rates would not be an issue as far as the FPGA is
concerned.  You still have the ability to shift individual clocks in 15 
degree
steps at 400 MHz.

The issue is 'What is the real performance of the A-D?'  Are they all really
sampling consistently where you want them to?  Run at maximum
specification speed, they are only delivering an effective 14 to 14.5
bits of resolution.  Any errors in the sampling process would only
decrease that.

--- Graham

==

L. Van Warren wrote:
> Graham -
>
> What is the:
> 	- clock rate on an Alterra Cyclone?
> 	- sample rate of the fastest 16 bit ADC?
> 	- highest frequency one would want to process?
>
> Van / AE5CC / wdv.com
>
>
> -----Original Message-----
> From: Graham / KE9H [mailto:KE9H at austin.rr.com] 
> Sent: Thursday, August 20, 2009 10:43 AM
> To: L. Van Warren
> Cc: fallingstar at cauhf.org; hpsdr at openhpsdr.org
> Subject: Re: [hpsdr] Cascading ADC/FPGA Pairs
>
> L.Van:
>
> That is the beauty of using the FPGA.  For dedicated logic tasks
> like playing "put and take" with the output of several A->Ds, the
> FPGA is faster than a CPU, particularly one subject to continuous
> interruptions such as when a modern OS is involved.  The FPGA
> can do multiple things in parallel, as opposed to the one thing at
> a time, in series, that is characteristic of a CPU.  Note that the
> FPGA the oscilloscope company used is the same Cyclone-III
> family as HPSDR uses on Mercury.
>
> --- Graham
>
>  
>
>
>   


 1250810568.0