[hpsdr] Cascading ADC/FPGA Pairs

[L. Van Warren]

If you trace this conversation back, Graham doesn't answer the question,
which is what is the maximum clock rate of an appropriate FPGA, like the
Alterra Cyclone..

At some point, no matter how much parallelism is in the FPGA, the clock rate
of an FPGA-based system determines the maximum sampling rate of the signal.

My thought is that if a master CPU running at 3.5 GHz can coordinate the
final results of a set of slaved (and less expensive) FPGA/ADC pairs then it
is the clock rate of the CPU and not the FPGA which determines the maximum
sampling rate of the system.

Whether this is true I don't know, but that is the question that I want to
see the math for.

- Van / AE5CC / wdv.com




-----Original Message-----
From: John Nordlund [mailto:ad5fu at earthlink.net] 
Sent: Friday, August 21, 2009 2:31 PM
Cc: L. Van Warren; fallingstar at cauhf.org
Subject: Re: [hpsdr] Cascading ADC/FPGA Pairs

even better.. 

Graham / KE9H wrote:
> L.Van:
>
> That is the beauty of using the FPGA.  For dedicated logic tasks
> like playing "put and take" with the output of several A->Ds, the
> FPGA is faster than a CPU, particularly one subject to continuous
> interruptions such as when a modern OS is involved.  The FPGA
> can do multiple things in parallel, as opposed to the one thing at
> a time, in series, that is characteristic of a CPU.  Note that the
> FPGA the oscilloscope company used is the same Cyclone-III
> family as HPSDR uses on Mercury.
>
> --- Graham
>
> ==
>
> L. Van Warren wrote:
>> ***** High Performance Software Defined Radio Discussion List *****
>>
>> That was a very interesting post about using multiple low cost ADCS
>> to look
>> like a higher rate ADC.
>>
>> I'm wondering if a high-end CPU, running at say 3 GHz could
>> coordinate the
>> traffic coming from multiple ADC/FPGA pairs.
>>
>>
>>  
>>> From: alex <ajbr at btconnect.com>
>>> To: hpsdr at openhpsdr.org
>>> Subject: Re: [hpsdr] Cascading A/D Converters
>>>     
>>
>>  
>>> no i think that it would work, you divide the 1ghz into 5 so you
>>> have 40
>>>     
>> MHz at 72 deg phase, so > each ADC did every 5th sample
>>
>>  
>>> you would need a FPGA that worked at 1ghz though
>>>    
>>>> rstasiak at sympatico.ca wrote:
>>>>      
>>>>> ... blog which describes a process of cascading five Analog Devices
>>>>>         
>> AD8298-40 (40 MHz) dual   
>>>>> ADC's under the control of an Altera FPGA to get a 1 GHz sample rate
>>>>>         
>> system.  
>>>> 73  Alberto  I2PHD
>>>>       
>>
>>
>> Van / AE5CC / wdv.com
>>
>>
>>
>>
>>
>>
>>
>>
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>
>


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