[hpsdr] Cascading ADC/FPGA Pairs

[Graham / KE9H]

Hi Van:
I resent you a copy, offline, of my email from yesterday where I think I 
answered
your questions. So, what you can get out of a highly parallel FPGA
managing 5ea. 16 bit A->D converters is  5x16=80 bits of info at
200 MegaSamples per second, which I don't think the downstream
signal processing will care is in that format versus 16 bits at 1000 
MegaSamples
per second, since one of the early things you do with it is decimate it.

I am guessing that one FPGA could handle more
A-D's if the number of available phase steps is adequate.  The issue is more
likely the smearing of values in time in the front end of the A->Ds since
they were designed to sample 5 or 6 ns wide samples, and we would be
asking them to sample 1 ns wide samples.

--- Graham

==

L. Van Warren wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> If you trace this conversation back, Graham doesn't answer the question,
> which is what is the maximum clock rate of an appropriate FPGA, like the
> Alterra Cyclone..
>
> At some point, no matter how much parallelism is in the FPGA, the clock rate
> of an FPGA-based system determines the maximum sampling rate of the signal.
>
> My thought is that if a master CPU running at 3.5 GHz can coordinate the
> final results of a set of slaved (and less expensive) FPGA/ADC pairs then it
> is the clock rate of the CPU and not the FPGA which determines the maximum
> sampling rate of the system.
>
> Whether this is true I don't know, but that is the question that I want to
> see the math for.
>
> - Van / AE5CC / wdv.com
>
>
>
>
> -----Original Message-----
> From: John Nordlund [mailto:ad5fu at earthlink.net] 
> Sent: Friday, August 21, 2009 2:31 PM
> Cc: L. Van Warren; fallingstar at cauhf.org
> Subject: Re: [hpsdr] Cascading ADC/FPGA Pairs
>
> even better.. 
>
> Graham / KE9H wrote:
>   
>> L.Van:
>>
>> That is the beauty of using the FPGA.  For dedicated logic tasks
>> like playing "put and take" with the output of several A->Ds, the
>> FPGA is faster than a CPU, particularly one subject to continuous
>> interruptions such as when a modern OS is involved.  The FPGA
>> can do multiple things in parallel, as opposed to the one thing at
>> a time, in series, that is characteristic of a CPU.  Note that the
>> FPGA the oscilloscope company used is the same Cyclone-III
>> family as HPSDR uses on Mercury.
>>
>> --- Graham
>>
>> ==
>>
>> L. Van Warren wrote:
>>     
>>> ***** High Performance Software Defined Radio Discussion List *****
>>>
>>> That was a very interesting post about using multiple low cost ADCS
>>> to look
>>> like a higher rate ADC.
>>>
>>> I'm wondering if a high-end CPU, running at say 3 GHz could
>>> coordinate the
>>> traffic coming from multiple ADC/FPGA pairs.
>>>
>>>
>>>  
>>>       

 1250889746.0