[hpsdr] Cascading ADC/FPGA Pairs

[Phil Harman]

Hi Van,

Thanks for a most interesting discussion.

> Thus a new question is generated. What is the SDR analog of dual-ported
> video ram?
>

Well in an FPGA its called dual-ported RAM and its very easy to implement. 
We use many of these in the form of dual clock FIFOs in the various FPGAs 
that form HPSDR.

One comment I am interested in

>A major reduction in  signal to noise ratio is the consequence of trading 
>decimation for tiered
> averaging.

The S/N gain due to decimation is easily determined from the ratio of the 
input and output clock rates.   If instead of a conventional DDC (i.e. 
CORDIC,  CIC stages  then a Compensating FIR ) what order of S/N improvement 
can we expect from tiered averaging and how is this calculated?

Given the option of implementing a DDC in an FPGA or a high order FFT then 
I'm hoping there are substantial gains that result from the effort required 
to implement the latter :-)

73's Phil...VK6APH


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