[hpsdr] Cascading ADC/FPGA Pairs: Tiered Averaging S/N

[L. Van Warren]

> what order of S/N improvement can we expect from tiered averaging and how
is this calculated?

Let's try for a ballpark first order estimate. First some assumptions:

1) RF sample buffer size is a power of two, for example 2^16 = 65536 RF
voltage samples per buffer.
2) We are digitizing this buffer using a dynamic voltage range spanning 16
bits using a logarithmic level mapping and AGC. This does the best to manage
lightning bolts and QRP. 
3) We are filling this buffer 65536 times per second, sampling the spectrum
at 4.295 GHz.
4) We are recovering an underlying signal whose maximum frequency of
interest is 65,536 Hz.
5) Decimation only uses 1 sample in every 65536, the rest of the information
is discarded.
6) Tiered averaging trades time for space. It requires a tree of 16
intermediate buffers, each half the size of the previous, to accept the
result from averaging pairs of samples.
7) Initially the samples are not weighted by their position in the time. For
some applications the samples will be Gaussian weighted corresponding to
their offset time.
8) When two samples are averaged the signal to noise is cut in two. If you
cut the noise in half, sixteen times, what do you get? At 3.0103 dB a pop,
that's a 48+ dB noise reduction.

Obviously this is idealized since we don't have single ADC's that will do
this yet. Creating same from a set of FPGA/ADC nodes is what gave rise to
the calculation. I have built a spreadsheet that lets you play with the
assumptions and calculates the resulting noise reduction and hardware
implications. One result is that using a 4 byte floating point value for
voltage only doubles the buffer footprint. Another result is that tiered
averaging reduces noise by 27 dB for current SDR, weighted buffers not
withstanding. These figures are theoretical, your results may vary.

Spreadsheet at                      http://tinyurl.com/ku8wtk

Two recent developments are on our side:
1) die on silicon circuit boards    http://tinyurl.com/nzdsoy
2) C to FPGA:                       http://tinyurl.com/kw8lce

Van / AE5CC / wdv.com



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