[hpsdr] Cascading ADC/FPGA Pairs Tiered footnote

L. Van Warren van at wdv.com
Fri Aug 28 13:05:19 PDT 2009


BTW - The Dan Tayloe converter used in the Softrock solves this problem by
using a pseudo analog to analog converter, and the noise floor is low
because the effect of the sample and hold is to filter the samples in the
analog domain prior to discretization.


 1251489919.0


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