[hpsdr] Verilog Class

[Kirk Weedman]

I will not be able to hold a Verilog class this coming Monday.  I should 
be able to resume on Thursday at 3:30PM PST.  We will continue with our 
discussion of OneWire code before Lecture #9.  There are only 2 lectures 
left and after those we can pick topics/areas of interest.  Be thinking 
about what you would like to do/hear/learn in a presentation.  In these 
final two lectures (#9 and #10) I will be covering RTL coding methods 
for synthesis, clocking issues, metastability, clock domain crossing, etc..

Thanks
Kirk Weedman  KD7IRS

 1235778640.0