[hpsdr] Verilog Class

[Georg Prinz]

Hello Kirk,

referring to "OneWire_rcv" code:

- for me, the way how SYNC-BIT is defined is something unusual. I
remember that in industry application always 7 sync-bytes with following
pattern "10101010" were used. What was the reason to choose your
bit-pattern for logic 0/1?

- Did you made the delay calculation for the HPSDR-code you are
presenting?

As a proposal for a topic of interest would be to go shortly through the
mercury Verilog code. First to get an overview what functions are
implemented on mercury and to get an idea how e.g. the filters, the
decimation etc. are done there. 

Best Regards

Georg, dl2kp



On Fr, 2009-02-27 at 15:50 -0800, Kirk Weedman wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> I will not be able to hold a Verilog class this coming Monday.  I should 
> be able to resume on Thursday at 3:30PM PST.  We will continue with our 
> discussion of OneWire code before Lecture #9.  There are only 2 lectures 
> left and after those we can pick topics/areas of interest.  Be thinking 
> about what you would like to do/hear/learn in a presentation.  In these 
> final two lectures (#9 and #10) I will be covering RTL coding methods 
> for synthesis, clocking issues, metastability, clock domain crossing, etc..
> 
> Thanks
> Kirk Weedman  KD7IRS
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