[hpsdr] Verilog Lecture 1

[WBR/WF4R]

Hello Mike, et all,
Audio was excellent.  Unfortunately I was not able to get it real time.  So far I've understood everything presented.  
Just want to let you know that I appreciate what you're doing.
The pace of the lecture seemed just a bit fast, but that may be because I'm not used to being in school lately.  The advantage of being able to get the lecture in non real time is that I can pause it I need to.

The mouse cursor was visible, and again the audio was good quality.

My objective in learning VHDL is to possibly synthesize a TTL project into one Verilog chip.  That would be really cool (if I could actually do it).  Hopefully I learn enough to get started on that project.

Looking forward to getting the simulator and doing the labs.  I'm a white rabbit, I'm way behind.

73, Bill, wf4r
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