[hpsdr] [Fwd: Re: Penelope transmit timing after PTT

[David McQuate]

Here's how I read the Verilog code, schematics, etc--

PTT from penelope mic connector or DB25 pin 1 is used to set Atlas bus 
line C15.
Ozy debounces C15 and sets a bit in the Command & Control data sent via 
USB to the PC.

The PC software (say PowerSDR) sets a bit in the Command & Control data 
sent via USB
back to OZY, and thence to Penelope, where it is used to turn on the PTT 
FET whose drain
is connected to DB25 pin 13.  The transfer of PTT state from USB data 
received by the PC
to USB data sent from the PC is probably fairly quick, but may depend on 
the selected
sampling rate.  The PTT bit is sent with every USB packet or frame
(whatever you want to call it) of 512 bytes.

Penelope produces RF output whenever the PC sends non-zero I and Q data 
to it, which will
begin shortly after the PC receives the PTT active indication.  When not 
transmitting, the PC
always sends zeros.  In the case of CW transmission,
the I & Q data sent to penelope are generated by the PC.  For SSB, the I 
& Q data are
calculated from digitized Mic data received by the PC from penelope or 
janus.  The calculation
takes a finite amount of time, so the generation of RF output will be a 
bit delayed, depending on
the length of the DSP buffers used on the PC.

If the PC software supports VOX operation, the PC will activate PTT sent 
to penelope.  It's likely
that the PTT FET will be activated before any RF is produced, but I'm 
not sure by how long.

Please correct me if there are inaccuracies in what I've written.

Dave
wa8ywq
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