[hpsdr] Call for Comments and Discussion - OzyII

[Phil Harman]

All,

I've posted a preliminary block diagram of what  OzyII could look like on 
the Wiki -

< http://openhpsdr.org/wiki/index.php?title=OZYII >

It's basically a large, leaded, FPGA connected to a 10/100/1000 Ethernet PHY 
chip.  The LVDS transceivers will provide high speed data access to Mercury 
and other future projects to free us from any Atlas bus limitations.

There are a number of options for the Gigabit PHY, these are shown on the 
Wiki. Initially I'm trying to avoid those manufacturers that require an NDA 
before they will release data sheets etc on their chips.  If anyone has 
experience with such PHYs  I would be grateful to hear from them.

By using a large FPGA if offers the potential to add a soft core 
microprocessor in the future so that the board can run a full TCP/IP stack, 
UDP etc. e.g. uIP (see  http://www.sics.se/~adam/uip/index.php/Main_Page ).
Initially we will use the Gigabit PHY as just a fast connection to the PC 
and use raw frames to communicate.

Lyle, KK7P, has kindly volunteered to lay out the PCB and we have funding 
from TAPR to undertake the prototype development.  Thanks to both for their 
continued support.

Bill, KDTFD, has offered to help with the PC Ethernet code and would 
appreciate assistance from anyone who has experience with working with 
Ethernet at a low level on the PC under Windows.

Feedback is requested in relation to features and facilities that folks may 
require.

73's Phil...VK6APH






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