[hpsdr] Call for Comments and Discussion - OzyII

[Dan Quigley]

Phil, I really like the idea of using Ethernet. For this comment I'm
assuming that that the intent for the initial release of OzyII is to use
layer 2 for the Ethernet connection to the PC.   

Most network switches operate at the data link layer (layer 2 in the OSI
model) which would mean you could use most common switches or a xover cable.
There are some switches that operate at layer 3, but those are not common in
consumer grade switches.

On the FPGA, are you're thinking to initially implement a full layer 2
interface to take advantage of error notification and flow control? And that
the higher, routable levels (IP/TCP/UDP etc) could be added at later time.
If so you may want to 

This design doesn't necessarily require a dedicated second NIC on the PC,
unless people decide forgo a switch and use a xover cable. There may be
additional performance limitations to a single-NIC approach, like doing
massive concurrent LAN data transfers and using HPSDR concurrently. The
design doesn't exclude those that want or need a dedicated NIC.

On the PC end of the connection, to access layer 2 data, we'll need
something that speaks NDIS and can filter packets. Winpcap (www.winpcap.org)
is free, open bsd, and would be good enough, however, they don't quite yet
have full featured support for Vista and Windows 7.  Code written for
winpcap is fully compatible with libpcap, which eases Linux portability.
There are also a ton of network tools and sniffers that use the winpcap
libraries which could help during dev, debug and installation.

Wish:
How much trouble and cost would there be to include (or allow for an
optional) USB 2.0 host interface in this design? That would make off the
shelf I/O, storage and memory "easier" to integrate.

Dan (N7HQ)

-----Original Message-----
From: hpsdr-bounces at lists.openhpsdr.org
[mailto:hpsdr-bounces at lists.openhpsdr.org] On Behalf Of Phil Harman
Sent: Saturday, July 18, 2009 1:50 AM
To: hpsdr at openhpsdr.org
Subject: [hpsdr] Call for Comments and Discussion - OzyII

***** High Performance Software Defined Radio Discussion List *****

All,

I've posted a preliminary block diagram of what  OzyII could look like on 
the Wiki -

< http://openhpsdr.org/wiki/index.php?title=OZYII >

It's basically a large, leaded, FPGA connected to a 10/100/1000 Ethernet PHY

chip.  The LVDS transceivers will provide high speed data access to Mercury 
and other future projects to free us from any Atlas bus limitations.

There are a number of options for the Gigabit PHY, these are shown on the 
Wiki. Initially I'm trying to avoid those manufacturers that require an NDA 
before they will release data sheets etc on their chips.  If anyone has 
experience with such PHYs  I would be grateful to hear from them.

By using a large FPGA if offers the potential to add a soft core 
microprocessor in the future so that the board can run a full TCP/IP stack, 
UDP etc. e.g. uIP (see  http://www.sics.se/~adam/uip/index.php/Main_Page ).
Initially we will use the Gigabit PHY as just a fast connection to the PC 
and use raw frames to communicate.

Lyle, KK7P, has kindly volunteered to lay out the PCB and we have funding 
from TAPR to undertake the prototype development.  Thanks to both for their 
continued support.

Bill, KDTFD, has offered to help with the PC Ethernet code and would 
appreciate assistance from anyone who has experience with working with 
Ethernet at a low level on the PC under Windows.

Feedback is requested in relation to features and facilities that folks may 
require.

73's Phil...VK6APH





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