[hpsdr] Call for Comments and Discussion - OzyII

[Steven Wilson]

I've been reading everyone's comments and I wanted to throw a few points
your collective way since I build SOC's for a living.

If you want to make a soft SOC in the FPGA we need to add several pieces.
1) External Flash memory for code storage (the OS goes there..)
2) SDRAM (cheaper) or DDR so that there is sufficient RAM for the OS to
do it's thing.
Bottom line - don't depend on the FPGA resources for code storage.
3) JTAG port OTHER than the download port to debug the processor.
4) A soft processor built to go into an FPGA.
5) A UART port for debug messages (already got provisions for that..)

Things to consider
1) A soft processor in an FPGA is NOT going to be fast.  Example - an
ARM7 can do maybe 30-40Mhz in an FPGA.
2) Since you have a slow processor - don't expect it to drive a 1Gb Enet
at 1Gb!  That begs the question - why 1Gb Enet? Isn't 100Mb going to be
fast enough for you since you can't possibly generate traffic at 1Gb
speeds with the soft CPU.
3) There are ports of uCLinux to things like the NIOS that already have
TCP/IP stacks -so you don't have to re-invent the wheel. The trick would
be to try and use someone else's example SOC as a basis for what you
create that already has uCLinux ported to it. MUCH less work that way.

I think that covers it.

Steve KA6S


Phil Harman wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> All,
>
> I've posted a preliminary block diagram of what  OzyII could look like
> on the Wiki -
>
> < http://openhpsdr.org/wiki/index.php?title=OZYII >
>
> It's basically a large, leaded, FPGA connected to a 10/100/1000
> Ethernet PHY chip.  The LVDS transceivers will provide high speed data
> access to Mercury and other future projects to free us from any Atlas
> bus limitations.
>
> There are a number of options for the Gigabit PHY, these are shown on
> the Wiki. Initially I'm trying to avoid those manufacturers that
> require an NDA before they will release data sheets etc on their
> chips.  If anyone has experience with such PHYs  I would be grateful
> to hear from them.
>
> By using a large FPGA if offers the potential to add a soft core
> microprocessor in the future so that the board can run a full TCP/IP
> stack, UDP etc. e.g. uIP (see 
> http://www.sics.se/~adam/uip/index.php/Main_Page ).
> Initially we will use the Gigabit PHY as just a fast connection to the
> PC and use raw frames to communicate.
>
> Lyle, KK7P, has kindly volunteered to lay out the PCB and we have
> funding from TAPR to undertake the prototype development.  Thanks to
> both for their continued support.
>
> Bill, KDTFD, has offered to help with the PC Ethernet code and would
> appreciate assistance from anyone who has experience with working with
> Ethernet at a low level on the PC under Windows.
>
> Feedback is requested in relation to features and facilities that
> folks may require.
>
> 73's Phil...VK6APH
>
>
>
>
>
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