[hpsdr] Call for Comments OzyII

[Larry Gadallah]

2009/7/28 J.D. Bakker <jdb at lartmaker.nl>:
>
> At 01:52 -0400 28-07-2009, jeff millar wrote:
>>
>> Someone made the point that the SDR architecture shouldn't worry about CPU
>> power because Moore's law will make it available shortly. But, that same
>> Moore's law will make for faster faster and wider A/Ds, faster and cheaper
>> FPGAs, and more complex signal processing algorithms.
>
> This assumes that you upgrade your HPSDR front-end as often as you upgrade
> your PC. I think it would be very useful for the average user to be able to
> have the current (not-so-cheap) hardware be somewhat future proof, and to
> get a performance boost by simply upgrading their computing backend. It's
> *software* defined radio, after all.
>
> Besides, Kirk's excellent Verilog tutorial notwithstanding it is not
> unreasonable to assume that much more people are comfortable programming on
> their computer than modifying an FPGA. I firmly believe that the 'smarts'
> for SDR should be on a PC, and that the main job for the front-end is to
> offer an adjustable pre-filter for the ADC stream so that slower PCs don't
> end up trying to drink from a firehose.
>
> JDB.
> [if you factor in development and upgrade costs, it's hard to keep up with
> COTS PC hardware bang-for-buckwise]

I strongly agree. The place where amateurs can really innovate is
unlikely to be in the hardware and/or system layout. It will be in the
creative uses of existing, practical and proven technology to
applications where they have not been applied (i.e. amateur radio
systems). This means FPGA firmware and PC/general purpose CPU
software.

The price/performance ratio of commodity PCs (and related) hardware
has been increasing steadily for a couple of decades now. To me, this
means that an SDR application that a current generation PC can barely
handle today will likely not be a problem in 12-18 months. Although we
are probably getting close to the end of this era, emerging
enhancements like using graphics cards as vector processors and
multi-core CPUs should drive it for a bit longer in spite of the
complications they introduce into the software.

Having said that, it is my understanding that Moore's law does not
apply at all in the same way to ADCs, which have to deal with the
unruly analog world. While there are some very real, hard limits to
what may be possible at the front-end (ADCs), I think we should be
thinking about designing systems to handle perhaps 18 bit, 250 MSPS
systems today, even though the best we can get now is 16 bits at 160
MSPS, and design the SDR-PC interfaces (i.e. GigE, USB 3, Firewire,
etc.) accordingly. I am not an expert, but I understand that there is
a very non-liner relationship between the power consumption of an ADC
and product of the number of bits of resolution and the sampling
speed. So, while we might like to see a 1 GSPS 32 bit ADC, nobody can
figure out how to funnel the kilowatt of power it will require into
the chip. We might expect some improvements on what we have for ADCs,
but the progress will be much slower than it is for all-digital
components like PCs, disk drives, etc.

-- 
Larry Gadallah, VE6VQ/W7                          lgadallah AT gmail DOT com
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