[hpsdr] Call for Comments OzyII

[J.D. Bakker]

At 01:52 -0400 28-07-2009, jeff millar wrote:
>Someone made the point that the SDR architecture shouldn't worry 
>about CPU power because Moore's law will make it available shortly. 
>But, that same Moore's law will make for faster faster and wider 
>A/Ds, faster and cheaper FPGAs, and more complex signal processing 
>algorithms.

This assumes that you upgrade your HPSDR front-end as often as you 
upgrade your PC. I think it would be very useful for the average user 
to be able to have the current (not-so-cheap) hardware be somewhat 
future proof, and to get a performance boost by simply upgrading 
their computing backend. It's *software* defined radio, after all.

Besides, Kirk's excellent Verilog tutorial notwithstanding it is not 
unreasonable to assume that much more people are comfortable 
programming on their computer than modifying an FPGA. I firmly 
believe that the 'smarts' for SDR should be on a PC, and that the 
main job for the front-end is to offer an adjustable pre-filter for 
the ADC stream so that slower PCs don't end up trying to drink from a 
firehose.

JDB.
[if you factor in development and upgrade costs, it's hard to keep up 
with COTS PC hardware bang-for-buckwise]
-- 
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lartmaker.nl/

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