[hpsdr] Technical question

[Phil Harman]

Hi Alberto,



  My questions are :

  1) Is that true ? In other words, are the ADC, DAC and FPGA clocks in the Mercury card all phase locked together ?

  Yes, all the clocks are derived from the master 122.88MHz clock

  2) If 1) is true, how should I behave when e.g. the  input data have a sampling frequency of 96 kHz ? Should I send
      an output frame every two input frames, or should I send the output frames at the same rates of the input ones,
      repeating the data if need be ?

  Always send the data at 48kHz, just discard data at higher rates. 

  Thanks

  73  Alberto  i2PHD
   



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