[hpsdr] FPGA Speed Grade on Ozy

[Doug Gibbs]

With reference to the Ozy problem with C7N & C8N parts, I had an 
experience earlier this year that may relate.  I had an Ozy/Janus/Atlas 
working with a softrock and wanted to play around with the Ozy FX2 
firmware and FPGA code. I downloaded and installed Eclipse and got it 
running to recompile the FX2 firmware successfully.  Then I downloaded 
Quartus and the Ozy2_Janus2 project for the FPGA.  It took me awhile to 
get the .v code to compile without errors due to setup and configuration 
problems, but I finally got it to work.  I could then successfully run 
initozy and both the firmware and FPGA code would load OK but when I ran 
PowerSDR, I did not have a spectrum display or any audio.  I pursued the 
problem for quite awhile but was unable to determine what was wrong.  
Finally, I was looking at the Quartus settings (for the 100th time) and 
noticed there were two entries for the Altera EP2C8Q208 FPGA.  One had a 
suffix of C7N and the other C8N.  The EP2C8Q208C8N was selected by 
default.  I checked the FPGA on my Ozy board and it was a C7N, so I 
selected that in Quartus.  The code compiled and when I initialized Ozy 
and started PowerSDR everything worked perfectly and has every since.  I 
have subsequently added Mercury and Penelopy and they have worked fine.  
My boards don't seem to be position sensitive in Atlas.

In my case, I was trying to compile for the C7N with C8N selected in 
Quartus.  I don't know what the effect would be if you compiled for the 
C7N and then used the code with a C8N.  Maybe someone that has a C8N can 
pursue it.  I don't know if any of this relates to the present problem 
but I thought I should mention it.

Doug - W8NFT




----- Original Message ----- From: "Scott Cowling" <scotty at tonks.com>


Subject:
[hpsdr] FPGA Speed Grade on Ozy
From:
Scott Cowling <scotty at tonks.com>
Date:
Wed, 03 Jun 2009 18:57:20 -0700

To:
<hpsdr at openhpsdr.org>


OK, here's the real story dug up from the paper archives.

Due to our supplier's inability to deliver enough Altera FPGAs in time 
for us to complete the Ozy build prior to Dayton in 2007, we purchased 
FPGAs from three different vendors.

162 of them were C7 speed grade
495 of them were C8 speed grade

Notice that the total is 657 even though we built only 650 boards. This 
allows a couple of spares.

So, up to 162 boards out there in HPSDR-land have the faster chip on 
them. Before you get to thinking that your board is better because you 
have the faster chip (or worse due to the slower chip), here are some 
figures for you from the Altera Cyclone II handbook regarding performance:

16-bit counter, f(max)
C8:  310.65MHz
C7:  349.4MHz

18x18 multiplier, f(max)
C8:  180.57MHz
C7:  216.73MHz

8-bit, 16-tap FIR filter, f(max)
C8:  110.57MHz
C7:  131.25MHz

Maybe Kirk can comment, but I don't think we are anywhere close to the 
f(max) limits on anything we do in Ozy. Of course, that does not mean 
that there isn't a bug that a faster FPGA "fixes".

Just like putting 667MHz SDRAM on your PC bus that runs at 533MHz, a 
faster FPGA does not run any "faster" just because it is a C7 instead of 
a C8. It only has to be "fast enough" to keep up with the clock given 
the internal logic that is programmed into it.

It would be informative to see if anyone has a C7 FPGA that exhibits the 
bug.

Also note that FPGAs run marginally slower when they are hot. If the 
problem is right on the edge, that might explain why the boards work for 
a while and then degrade after they heat up.

Welcome to the "fun" world of FPGA debug! Hope this is somewhat helpful.

73,
Scotty WA2DFI

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