[hpsdr] Ozy and the new code release

[Keith]

Hi Kirk,
I do have the audio distortion and Ozy is a C8N. 
I'm using SVN Build 3166 of PSDR
Ozy Fx2 20090524
Ozy 14
Mercury 27
Penelope 12

At power on D1 is off
Run initozy11 and D1 flashes 0100 repeatedly Start PSDR D1 completes the
0100 and then is off Stop PSDR D1 flashes 0000 repeatedly Reloading
initozy11 and D1 flashes 0100 repeatedly

I do have a question I have been looking at the code for the Ozy project  I
set all the compile options I could find in the code but I keep getting this
critical warning after the compile "Critical Warning: (High) Rule D101: Data
bits are not synchronized when transferred between asynchronous clock
domains. Found 69 asynchronous clock domain interface structure(s) related
to this rule." Imagine I haven't met a pre-compile condition just not sure
what that is or how to figure out what it is, the three clock domains I have
found so far are still pretty much a mystery to me. 

I'm going to go look at the code you mentioned in the email to see if I can
figure out what all the flashing is about...Thanks for working on the
project it is very much appreciated. Let me know if you need any other info.

-----Original Message-----
From: hpsdr-bounces at lists.openhpsdr.org
[mailto:hpsdr-bounces at lists.openhpsdr.org] On Behalf Of Kirk Weedman
Sent: Sunday, June 14, 2009 1:38 PM
To: hpsdr at lists.openhpsdr.org
Subject: [hpsdr] Ozy and the new code release

***** High Performance Software Defined Radio Discussion List *****


I would like to gather some information on the new FPGA code release.  
LED D1 flashes a code under certain conditions.  If D1 is flashing 
please send me the code which I will explain below, which version of 
FPGA (C8 or C7), which boards are installed, and whether you have any 
audio or other problems.  This may help me determine some issues in the 
design.  I would like this info from people that ARE having problems and 
people that ARE NOT apparently having problems.

Code:  D1 flashes a 4 bit value.  Least significant bit is flashed first

Here's what a value of 0 looks like
            +---+           +---+           +---+           +---+
D1 ---------+   +-----------+   +-----------+   +-----------+   
+-----------+------------------------
                0 (LSB)             0               0               
0         dead time between 4 bit flashes
Here's what a value of 4 looks like

            +---+           +---+           +----------+    +---+
D1 ---------+   +-----------+   +-----------+          +----+   
+-----------+---------------------
                0                  0                1               0

More details can be seen near the bottom of the ozy_janus.v code if 
interested.

Thanks
Kirk KD7IRS
_______________________________________________
HPSDR Discussion List
To post msg: hpsdr at openhpsdr.org
Subscription help:
http://lists.openhpsdr.org/listinfo.cgi/hpsdr-openhpsdr.org
HPSDR web page: http://openhpsdr.org
Archives: http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/
No virus found in this incoming message.
Checked by AVG - www.avg.com 
Version: 8.5.339 / Virus Database: 270.12.68/2175 - Release Date: 06/14/09
05:53:00


 1245019681.0