[hpsdr] Verilog Class lab 5.1

[Georg Prinz]

Hello Kirk,
going through lab 5.1 following question arose:

Creating a separate module STACK for the DESIGN module there is no loop
anymore to call STACK PILE(...);

Further more, during the Test the STACK module is not called either.

This is also a question of how far a variable is valid in the hierarchy?

E.g. POP is defined within module DESIGN and updated under module STACK.

Maybe I am still looking at Verilog from a serial working programming
language.

Vy73, Georg, dl2kp