[hpsdr] Verilog Class

[Georg Prinz]

Hello Kirk,
I wonder, that I am the only one with questions concerning the classes.
Nevertheless, refering to Lab. 8.1 and 8.2 I have following questions:

- The 16MHz-clock-generator has a deviation of 0.81%, that means
16.129MHz. I tried a delay with 62.5ns, but failed. Obviously it is not
possible to choose decimal parts. Is it feasible to choose a time
resolution of ps instead and a delay 62500ps. Or, you agree that for
simulation purposes it doesn't matter to have a slightly different
frequency?

- In Lab 8.2 there is a print out of the P&R tool (What does P&R mean?).
Is this tool a vendor specific tool or a general one? Is it used for
HPSDR?

Vy73, Georg, dl2kp




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