[hpsdr] Verilog class

[Kirk Weedman]

For those of you that are taking the Verilog class, I have now upgraded 
my designs to use the free Altera Quartus 9.0 web edition tools which 
you can download and use to compile my latest code that I've posted on 
the verilog.hpsdr.org website.  I have also inlcuded my latest Penelope 
code though I havent done much debugging on it.  I am hoping others will 
use this as a way to become involved in learning the HPSDR FPGA code for 
Mercury, Ozy and Penelope and others as time goes on.  In the current 
projects you should be able to compile, check reports, determine what 
the warnings mean, look at project assignments of various types and 
experiment with the SignalTap tool as discussed in the last lecture (now 
posted on the website).  You should also practise/learn how to program 
Mercury, Ozy and Penelope via the JTAG connectors using a USB Blaster or 
Byte Blaster and at least get Ozy and Mercury running and tuned to a 
station with this new code.  There is more that needs to be done but its 
a start.

Hope to see more people become involved in debugging this latest "test" 
code.  I will release some simulation testbenches for Ozy before long so 
you can do simulations of Ozy and help debug that way too.  You can then 
compare internal FPGA signals using SignalTap with those in the simulation.

I hope this is starting to become more interesting now.

Thanks
Kirk  KD7IRS

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