[hpsdr] Hermes design thoughts

[Steven B. Dick]

Allow me to introduce myself.  I'm Steve, K1RF.  I'm an electrical engineer
over 40 years but in the management chain now.  While I'm not a verilog or
VHDL programmer or softrware programmer, I know enough to get by and I
understand and appreciate different architectual concepts. I recently became
totally fascinated by the software defined radio concept.  I've been
following the HPSDR Wiki for awhile.  I was actually considering taking
ideas from prior HPSDR projects to make a simple transceiver pc board and lo
and behold, I came across Hermes and Apollo hidden somewhat down at the
bottom of the wiki page. Wow! Right along the lines I was thinking.  I
looked at the schematic and loved it.  The only main thoughts I have on it
now are in two areas.  One is the front end, the other is to add Verilog
code in the FPGA to allow, along with a simple 2-line alphanumeric display
and some controls, a totally self contained transceiver without the need for
a PC. It could have two modes of operation, the standard mode using an
external PC with communication over USB or Ethernet for full capability, and
a self-contained mode. Transmitter code concepts would be along the lines of
the Digimit transmitter (See http://www.microtelecom.it/digimit/ with more
on SSB modulator architecture defined in detail at
http://microtelecom.it/ssbdex/.  The amount of FPGA firmware for the
transmit function would be fairly modest and should easily fit with room to
spare. Additional code would be needed for a self-contained basic receiver
without the full capabilities of the PC based software.
 
With regard to the front end, I saw a lot of discussion about preamp vs no
preamp, etc. I also looked at a QS1F front end discussion. My conceptual
design would have used a 1.6MHz high pass filter (always in) to eliminate
strong AM broadcasts if you happen to live near one) followed by a 60MHz
high pass filter (always in) followed by a programmable 0-31.5db HMC472
Hittite attenuator which allows 0.5dB attenuation steps followed by a
mini-circuits GALI-74+ preamp (always in) followed by a 6dB resistive pad
attenuator to cut the gain down some on the high gain preamp.  This would
eliminate any relay switching, provide finer control of RF attenuation while
trading off maximization of IP3 (would need additional FPGA I/O and
associated firmware).  I would not add any other filters,  to minimize
complexity and to depend on the inherent filtering of the antenna itself. I
would not add any filter switching, to keep things simple.  I prefer
simplicity to having ultimate control of switching things in and out.  I'd
rather have one smoothly continuous RF knob like in the old days.
 
Ultimately, it would be nice to have a DSP chip on the transceiver board to
allow future software coding to replace the external PC with an internal
high performance processor, and a more sophisticated front panel with a dot
matriz graphics display.  I envisioned all these as a growth options using
the PC initially but eventually switching over to the DSP chip and high end
front panel. One could keep both paths available for future software
development and providing a high performance, self-contained capability.
 
So those are my thoughts.
 
Regards,
 
Steve, K1RF 
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