[hpsdr] Penelope Firmware Upgrade: "Programming hardware cable not detected"

Thierbach, Ed ethierba at umich.edu
Fri Aug 6 07:16:33 PDT 2010


I haven't upgraded Penelope yet, so this is just theory, but here goes.  Do you have a Magister board, and have you placed jumpers on the I2C pins?  That may not have anything to do with it, since Penelope works fine (except for mic audio) without those jumpers.  

When you do find the problem, please consider posting it in the Penelope_Troubleshooting wiki page, or pass the info on to me and I'll add it.

73,
-Ed- AB8OJ

> -----Original Message-----
> From: hpsdr-bounces at lists.openhpsdr.org [mailto:hpsdr-
> bounces at lists.openhpsdr.org] On Behalf Of Jack Speer
> Sent: Friday, August 06, 2010 10:09 AM
> To: hpsdr at openhpsdr.org
> Subject: Re: [hpsdr] Penelope Firmware Upgrade: "Programming hardware
> cable not detected"
> 
> ***** High Performance Software Defined Radio Discussion List *****
> 
> 
>    Good, glad to know that's the right one.
> 
>    Does anyone have any ideas on the error
> message?  Penelope is dead in the water until I
> can figure out what's causing the error.
> 
> 
> 73,
> 
> Jack, N1BIC
> 
> 
> At 04:10 PM 8/5/2010, Kjell Karlsen wrote:
> >Hi Jack.
> >
> >Yes, JP7 (Last JTAG) is the one you found.
> >
> >73, Kjell
> >
> >
> >
> >
> >På Thu, 05 Aug 2010 21:51:13 +0200, skrev Jack Speer <speerj at buck.com>:
> >
> >>***** High Performance Software Defined Radio Discussion List *****
> >>
> >>
> >>Hi,
> >>
> >>    I have a Penelope board purchased from a gentleman in Germany on
> >>eBay.  I'm having trouble programming it.  After picking "B.  Program
> >>using Penelope_v1.2" (which I assume is right?) I get the message
> >>"Error:  Programming hardware cable not detected"
> >>
> >>    I've tried this with Quartus 9.1sp2 and Quartus 10.0.
> >>
> >>    One possibility, the HPDSRWiki instructions refer to placing a jumper
> >>on JP7 on Penelope, but there are no jumper markings on my board.
> From
> >>a fuzzy photo of another Penelope my best guess is JP7 was at the lower
> >>left corner of the FPGA, is that correct?
> >>
> >>
> >>Thanks,
> >>
> >>Jack, N1BIC
> >>
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> >
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