[hpsdr] OzyII schematic available for peer review

[Nick Massey]

Phil,

Some totally non-expert comments/questions ...

1. If U3 is 2V5 then shouldn't R3 be smaller. (Worst case Vf for D2 is 
2.4V.)

2. I don't expect is matters but J1 pin A12 is mis-labelled as A12A.

3. Is it correct that AVDDH and AVDDL on U8 are decoupled to the "three 
bars" (digital?) ground rather than the "triangle" (analog?) ground?

4. There is a confusing "cross-over" close to R38. It looks as if U10 1Z 
joins to 2B.

5. R41 and R42. I don't know how you've programmed the FPGA or what you're 
planning to connect here but we usually pull logic level RS232 signals high 
rather than low since that's the way they conventionally idle.

6. Are the OUT0 - OUT3 pins always defined as driven outputs? (Or can they 
be undefined or inputs during initialisation etc.?) If it's possible for 
them to float then perhaps pull-downs are needed to commit the outputs seen 
by the outside world?

7. I have no idea why there are LEDs on the RAM - but given that there are - 
is it correct that they are lines A0-A7, A10-A12 and IO4?

I'm really looking forward to OzyII - I can't work out where you find all 
the time!

Nick, VA7NRM

----- Original Message ----- 
From: "Phil Harman" <phil at pharman.org>
To: "OpenHPSDR (open)" <hpsdr at openhpsdr.org>
Sent: Saturday, May 22, 2010 8:42 PM
Subject: [hpsdr] OzyII schematic available for peer review


> ***** High Performance Software Defined Radio Discussion List *****
>
> All,
>
> V1.0 of the OzyII schematic is available for peer review.  The document is 
> available on the Wiki here:
>
> < http://openhpsdr.org/wiki/index.php?title=OZYII >
>
>
> Note that if you click on a component a descriptive box opens showing full 
> details of the particular component.
>
> Detailed checking of the schematic by others  will be greatly appreciated 
> in order to reduce the potential for errors in the Alpha PCB.
>
> Comments, corrections and suggestions via the openHPSDR reflector please.
>
> 73's Phil...VK6APH
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