[hpsdr] PowerSDR v1.19.3.1.diversity10 (K5SO 6OCT2010)

[Joe Martin K5SO]

Gerd,

RRR, okay,very  good!  I apologize that I misunderstood your problem  
and bombarded you with such detail, but, on the other hand, I'm very  
glad to hear that you have the diversity program up and running okay.

I think Kirk Weedman (kirk at hdlexpress.com) might be the Verilog  
programmer you need help from (perhaps?).  If not, Phil VK6APH can  
certainly direct you to the appropriate person.

Good luck with that new clock frequency project!

73,  Joe K5SO

On Oct 11, 2010, at 1:45 PM, Gerd Loch wrote:

> Joe,
>
> there is a misunderstanding:
> I need to modify the FPGA code for the different clock frequency  
> 196.608 MHz
> and have to change clock division factors, decimation factors and
> accumulator width.
> I have no problem with the "normal" clock 122.28 MHz and have  
> diversity
> running. So I need some help from the guy that wrote the FPGA coding.
> I already got a message who is the one and probably will get help.
>
> Nevertheless thanks for your support.
>
> 73, Gerd
> DJ8AY
>
>
>

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