[hpsdr] Diversity reception w/dual Merc boards

[Joe Martin K5SO]

Hi Gerd,

RRR.  Your test results are convincing.  Nice work in sorting this out.

Now we'll have to ponder whether we can streamline the Verilog code  
any more, I suppose, if we want to push any harder.  Not what I wanted  
to hear but, hey, there it is.  It's at least beneficial to know how  
close to the limit we're actually running.  Thanks for your work!

Joe K5SO




On Oct 26, 2010, at 4:01 PM, Gerd Loch wrote:

> ***** High Performance Software Defined Radio Discussion List *****
>
> Hi Joe,
>
> that is what I suspected: I have 2 Receivers to be configured in the  
> FPFA
> code.
> You need not send it as I have already compiled all variants NR=1, 2  
> and 4.
> I think there is no doubt that I have a timing issue with clock  
> speed 196
> MHz: NR=1 is running, NR=2 is running with interrupts and cracks and  
> NR=4 is
> only producing noise.
>
> 73, Gerd
> DJ8AY
>
>
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