[hpsdr] HPSDR diversity

[wully]

Hi Joe


You suggest a direct connection of the 122.88MHz-Clock of Mercury 1 
(Master) to the Mercury 2 (Slave).

Why is it not sufficient, to drive both Mercuries by the 10MHz-Clock 
from C16 and then using the PLL on the FPGA to run both 122.88 
MHz-Clocks synchronously?

I think, that a direct connection is better. But is the PLL mechanism 
not sufficient to generate coherency?

73 de HB9EPU, Alfred

 1312613768.0