[hpsdr] HPSDR diversity

[Phil Harman]

Hi Wully,

Using the PLL to lock both 122.88MHz clocks will give exact frequency lock 
but not phase.  This is because the phase will take on an arbitrary value in 
order to lock to the 10MHz reference. Over time/temperature the phase will 
naturally vary - just as required, expected and intended.

If you feed one  122.88MHz clock to each board then the phase relationship 
between the signals from each board will be sensibly constant.  The LVDS 
transceiver connections on the top edge of each board are a simple way of 
reticulating one clock to multiple boards.

73 Phil...VK6APH


----- Original Message ----- 
From: "wully" <wully at bluewin.ch>
To: <hpsdr at openhpsdr.org>
Sent: Saturday, August 06, 2011 2:56 PM
Subject: [hpsdr] HPSDR diversity


> ***** High Performance Software Defined Radio Discussion List *****
>
> Hi Joe
>
>
> You suggest a direct connection of the 122.88MHz-Clock of Mercury 1 
> (Master) to the Mercury 2 (Slave).
>
> Why is it not sufficient, to drive both Mercuries by the 10MHz-Clock from 
> C16 and then using the PLL on the FPGA to run both 122.88 MHz-Clocks 
> synchronously?
>
> I think, that a direct connection is better. But is the PLL mechanism not 
> sufficient to generate coherency?
>
> 73 de HB9EPU, Alfred
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