[hpsdr] Pennylane drivelevel

[wully]

Hi Phil

I am trying to use the pennylane instead of the penelope. I am 
programming the interface by myself. For test purposes, I do the 
following: as soon as the TX-frequency is changed by the user program, I 
make the change and then I request the setting of the drivelevel by 
setting a logical txLevel_changed.
In the next control-out seqence, I set C0 to 0x12, C1 to 0x80 (half 
power, just for Test), C2 to 0 (no micboost, mic selected)
C3-C5 are all set to zero.

But starting TX, I don't see any power out of pennylane.

I have never programmed FPGAs up to now. I see
in penelope.v the lines:

wire [7:0] Drive_Level;     // Tx drive level

NWire_rcv  #(.DATA_BITS(8), .ICLK_FREQ(122880000), 
.XCLK_FREQ(122880000), .SLOWEST_FREQ(1000))
       p_ser (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), 
.xclk(C122_clk),
              .xrcv_data(Drive_Level), .xrcv_rdy(drive_rdy), 
.xrcv_ack(drive_rdy), .din(C18));

Is it correct, that this driveLevel is "stored" in the fpga, so that I 
don't have to repeat C0 at 0x12 to transmit?


When I apply IQ-Values != 0 , I don't see output from pennylane. So I 
don't yet understand, how the current DriveLevel is treated in the 
pennylane.

Any clarification is welcome.

73, Alfred