[hpsdr] Iambic Keyer in Verilog

[Phil Harman]

Hi Boris,

Short answer  - Yes!

Long answer – It’s not quite that simple.

If we implement an iambic CW keyer in the FPGA then we will need to also implement the entire carrier generation. In which case we will need to add a raised cosine profile, with adjustable timing for different speeds, to the leading and trailing edges of the CW signal.

The Tx CW offset will also need to be adjustable to suit the operators preference.  In addition the side tone volume will need adjusting as well as its frequency to suite preferences. It will also require a profile, which may be different to the RF one, so there are no ‘clicks’ in the side tone signal.  All these settings will need to be adjusted via additional Command and Control signals over the Atlas bus. 

All of this can be done for sure. But it is so much easier to write this in a high level language on the PC.  

With careful setting of the various buffers in PowerSDR, and using Metis instead of Ozy,  then my gun CW operator friends tell me that  latency is not really an issue. 

73 Phil... VK6APH 





From: Boris Njegic 
Sent: Sunday, April 08, 2012 4:21 AM
To: hpsdr at lists.openhpsdr.org 
Subject: [hpsdr] Iambic Keyer in Verilog

***** High Performance Software Defined Radio Discussion List *****




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Hi all,

I am not familiar with Verilog but is it possible to implement Iambic keyer like this in Metis? Would that resolve latency problem with CW?  

Regards,

Boris
9A5ATY
-- 
BNJ



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