[hpsdr] Metis ver 1.6 vs 1.7

[Joe Martin K5SO]

Bill, 

According to Phil's comment in the Verilog source code for Metis v1.7, this is the difference: 

"2012 Mar 22  - Fixed bug in wide spectrum code where data was discontinuous. Problem was that the NWire receiver was not decoding the very first word sent from Mercury. This caused the data to spread across consecutive 4k blocks.  NWire_rcv uses the first word to sync its sampling rate. Fix was to generate a 'fake' spd_rdy signal from NWire_rcv when sync first detected.  The architecture was changed so that when the wide spectrum FIFO is empty it requests 4096 words from Mercury. The empty signal sends a 'trigger' pulse to Mercury on Atlas C21. The trigger signal causes Mercury to fill its FIFO with 4k words and then send them to the spectrum FIFO on Metis. When full this signals Tx_MAC to read out 8 by 1024 byte blocks.  The trigger is only active when wide_spectrum is selected.

 - Released as V1.7"


73,  Joe K5SO


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