[hpsdr] Single chip SDRs

[Phil Harman]

There are a number of 'single chip' DDC SDR designs starting to appear on
the market.  These incorporate the digital front end of a DDC in a single
IC and follow the

ADC > NCO > CIC > FIR

architecture that we use in Mercury and Hermes.

Examples of these ICs are the LM97593 and AFE8220-Q1. Both these chips
incorporate dual DDCs which is a very nice feature.

These chips are intended to be used primarily in Cell site base stations
which have lesser requirements in relation to dynamic range and alias
rejection than a high performance HF receiver.

For example the LM97593 uses a 4th order CIC filter. This means that the
first alias will only be 45dB down if a 64.512MHz clock is used for a
final sampling rate of 192kHz. Once an alias signal has been generated it
can't be removed using the subsequent FIR filters.

Recent measurements on an SDR using this chip confirm this figure.

The AFE8220-Q1 uses a 5 stage CIC filter and can sample at 75MHz which
will improve the alias rejection.  However, it only provides a 16 bit
output which limits the dynamic range to 96dB. This figure has to include
any band noise so will be 10 to 20dB less in practice.

There will be applications where such chips are very useful but just be
aware of the limitations before building using these chips or purchasing
ready built boards on eBay.

Hopefully future generations of these ICs will be more suited to high
performance HF receiver construction.

On a more positive note, the new AD9253 Quad ADC could form the basis of a
4 receiver version of Mercury.

73 Phil...VK6APH





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