[hpsdr] Single chip SDRs

Thu Jan 19 21:12:56 PST 2012

I have been playing with the AFEDRI8201 for a couple of years now (the 
predecessor to the AFE8220), based on a board designed by Dr. John Schwacke. 
Since we live in the Charleston, SC area, we ended up calling it the 
Charleston Receiver (very clever, we are).   Some of the documentation can 
be found at www.amrad.org under SDR & DSP.  John's original work can be 
found at:  http://sdrtrack.drupalcafe.com/     A couple dozen of these 
boards have been made so far.

This receiver uses a small board with the '8201, a VGA, and some switches to 
bypass the VGA.  It then plugs into a Digilent Nexys2 FPGA board (Xilinx 
Spartan-3E), using two PMOD sockets.  John's original software ran using 
GNURadio under Linux, or he wrote a basic spectrum analyzer for Windows. 
I've added support to Quisk (both Linux and Windows) to run the Charleston 
board.  I'd like to add interfaces to Winrad, KISS, and PowerSDR someday....

The biggest issue was that the original sample clock oscillator ran at 
80MHz, NOT a multiple of 48k.  It was OK for John, as he used a 32k playback 
sample rate, but some of my PCs at the time did not have that rate.  Hence, 
I changed the oscillator freq to 76.8MHz (now an Si570).  I also made a few 
other small changes to improve performance.

I have been working on a newer design based on the '8220 and an AD9744 for 
an exciter.  The big limitations are that the ADCs are only 12-bit, and as 
Phil says, the I/Q samples outputs are only 16-bit.  Therefore, the overall 
dynamic range is somewhat limited.  Some of this can be made up for by 
external bandpass filters, and controlling the VGA in front of the chip.

I recognize that these are NOT high-performance, but they are less costly, 
and less complicated to use.  The code in the Nexys2 board for the 
Charleston board is not much more than a couple of FIFO buffers, and SPI and 
SSI interfaces to the '8201, and it uses the FX2 for USB interfacing to the 
host.  Originally, the Charleston board was costing less than $70 to 
duplicate, but TI has virtually stopped making the '8201 available, and its 
cost has jumped.  I believe the Digikey price for the AFE8220 was around $50 
or so the last time I checked, much more than the $15 or so I paid for the 
first '8201.  Plus, the Digilent Nexys2 went from $99 to $149 
(non-academic).  So, the reproduction cost has gone up quite a bit.

Now I'm looking at a board that has the '8220, AD9744, Xilinx Spartan-3E 
(500k, non-BGA), and Wiznet W5300 for 100bt interface to the host.  I'm not 
sure about USB interfacing, but am toying with sharing the FPGA in/outs 
between the W5300 and an FX2.  The FX2 is a nice way to "program" the FPGA 
(directly or the EEPROM).  I'm a total FPGA beginner, and learning Verilog 
has been a challenge, but fun.  I'm hoping to make a less-expensive DDC/DUC 
board with this combination of parts.  I believe this is the future, not 
QSDs/QSEs.  Right now, I'm beginning to learn about the W5300, and 
interfacing it to FPGAs.  Fun, fun, fun.  (Do I use a softcore, or not use a 
softcore???  Just a state-machine??  Oh boy.)

Anyway, that's what I am playing with when other projects don't get in the 
way, which all too often.
73s
Terry, WB4JFI

-----Original Message----- 
From: Phil Harman
Sent: Thursday, January 19, 2012 9:25 PM
To: hpsdr at lists.openhpsdr.org
Subject: [hpsdr] Single chip SDRs

***** High Performance Software Defined Radio Discussion List *****

There are a number of 'single chip' DDC SDR designs starting to appear on
the market.  These incorporate the digital front end of a DDC in a single
IC and follow the

ADC > NCO > CIC > FIR

architecture that we use in Mercury and Hermes.

Examples of these ICs are the LM97593 and AFE8220-Q1. Both these chips
incorporate dual DDCs which is a very nice feature.

These chips are intended to be used primarily in Cell site base stations
which have lesser requirements in relation to dynamic range and alias
rejection than a high performance HF receiver.

For example the LM97593 uses a 4th order CIC filter. This means that the
first alias will only be 45dB down if a 64.512MHz clock is used for a
final sampling rate of 192kHz. Once an alias signal has been generated it
can't be removed using the subsequent FIR filters.

Recent measurements on an SDR using this chip confirm this figure.

The AFE8220-Q1 uses a 5 stage CIC filter and can sample at 75MHz which
will improve the alias rejection.  However, it only provides a 16 bit
output which limits the dynamic range to 96dB. This figure has to include
any band noise so will be 10 to 20dB less in practice.

There will be applications where such chips are very useful but just be
aware of the limitations before building using these chips or purchasing
ready built boards on eBay.

Hopefully future generations of these ICs will be more suited to high
performance HF receiver construction.

On a more positive note, the new AD9253 Quad ADC could form the basis of a
4 receiver version of Mercury.

73 Phil...VK6APH

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