[hpsdr] Penelope Troubleshooting

[David McQuate]

Making excellent progress!
JP2 and JP3 pin 2 should have almost identical signals.  The filter 
consisting of L3, L5, L8 and associated capacitors are a low-pass 
filter, whose purpose is to block aliased signals (those between 55 MHz 
and 122 MHz) and, of course, the DAC clock frequency at 122.88 MHz.  
Since your scope BW is less than the clock frequency you won't see the 
clock on either side of the filter, so seeing similar voltages is to be 
expected.

The power LEDs 2 thru 6 on Penelope reflect the voltage at the output of 
U9B, as digitized to 12 bits by U16, and read over the SPI bus by the FPGA.
LED    digitized value
2 on if >  250
3 >  500
4 > 1000
5 > 2000
6 > 3000

As the positive peak voltage at the BNC connector (J5) increases, the 
detector voltage should rise (U9A pin 1 and U9B pin 7).  Check those 
pins with a DVM.  As you increase the drive setting in PowerSDR these 
voltages should rise.  If they do, but the LEDs do not light, seems like 
there's a problem with U16 or the SPI bus to the FPGA.

This digitized voltage, as well as those at pins 20 and 7 on the 25 pin 
connector, J6, are transmitted to the PC.  I'm not sure what value is 
used by PowerSDR to show power out.

73,
Dave
WA8YWQ

On 7/29/2012 4:49 PM, Stephen West-Fisher wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> After being a lot more careful with testing (and not paying attention to my
> power meter) I have a completely different set of problems. This evening I
> also updated from SVN all the code, which included the new 2.2 Ozy code. For
> completeness Penelope is at 1.7.
>
> I DO have output in TUN at the antenna!
> However, the power LEDs do not light and PowerSDR still shows 0 power out.
> All of the tests below appear to be fine.
> When I went back and checked pin 2 of JP2 and JP3 they both appear to have
> the same peak to peak voltage which I believe is not supposed to be the
> case.
> Any ideas of where to look for these issues?
>
> --
> Stephen West-Fisher
> N4IK
>
>
> -----Original Message-----
> From: hpsdr-bounces at lists.openhpsdr.org
> [mailto:hpsdr-bounces at lists.openhpsdr.org] On Behalf Of David McQuate
> Sent: Saturday, July 28, 2012 11:31 PM
> To: hpsdr at lists.openhpsdr.org
> Subject: Re: [hpsdr] Penelope Troubleshooting
>
> ***** High Performance Software Defined Radio Discussion List *****
>
> The fact that LED7 changes blink rate--to indicate PTT change--shows that
> the FPGA is at least partially alive and working properly.  If Bob's
> software / firmware suggestions don't take care of the problem, and you have
> an oscilloscope, you might carefully probe the DAC input data lines while
> TUN is active: bits 0 - 13 on U7 pins 14 - 1.  The lower bits should have
> high frequency square waves, the higher bits, lower frequency.  These are
> the digitized sine wave generated by PowerSDR to produce the CW TUNE signal.
> The clock input, U7 pin 28 should have a very fast square wave -- 8 ns
> period.  If they're changing, but there's no signal on JP3 pin 2, there's a
> problem with the
> DAC.   Check that pins 24, 25&  pin 27 are +3.3 volts.
>
> With TUN active, Atlas C19 should have digital signals--the transmit data--I
> &  Q data from the PC via Ozy.  The data is sent using "NWire", a digital
> pulse-width modulation, with a "0" represented by a short high pulse, and a
> "1" by a longer high pulse.  Thus when sending all zeros -- as when PTT or
> TUNE are not active -- there will still be many fast pulses, in bursts with
> a 48 kHz repetition rate.
>
> Atlas C20 should also have digital sgnals -- the command and control data
> broadcast by Ozy to Mercury&  Penelope.
>
> 73,
> Dave
> WA8YWQ
>
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Clear Stream Technologies


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