[hpsdr] Penelope Troubleshooting

[Stephen West-Fisher]

Yup, that was the problem. U16 was not getting a clock signal, everything is
working correctly now!

Thanks! And on to Mercury :-)
--
Stephen West-Fisher
N4IK


-----Original Message-----
From: Stephen West-Fisher [mailto:steve at coastaldatasystems.com] 
Sent: Sunday, July 29, 2012 9:53 PM
To: 'hpsdr at lists.openhpsdr.org'
Subject: RE: [hpsdr] Penelope Troubleshooting

Tomorrow I'll rework that side of the FPGA and see if that solves my
problem.

--
Stephen West-Fisher
N4IK


-----Original Message-----
From: hpsdr-bounces at lists.openhpsdr.org
[mailto:hpsdr-bounces at lists.openhpsdr.org] On Behalf Of David McQuate
Sent: Sunday, July 29, 2012 10:26 PM
To: hpsdr at lists.openhpsdr.org
Subject: Re: [hpsdr] Penelope Troubleshooting

***** High Performance Software Defined Radio Discussion List *****

As the positive peak voltage at the BNC connector (J5) increases, the
detector voltage should rise (U9A pin 1 and U9B pin 7).  Check those pins
with a DVM.  As you increase the drive setting in PowerSDR these voltages
should rise.  If they do, but the LEDs do not light, seems like there's a
problem with U16 or the SPI bus to the FPGA.

This digitized voltage, as well as those at pins 20 and 7 on the 25 pin
connector, J6, are transmitted to the PC.  I'm not sure what value is used
by PowerSDR to show power out.

73,
Dave
WA8YWQ


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