[hpsdr] Status Update For AJ6BC

[John Westmoreland]

HPSDR,

Sorry I missed the call yesterday.  Sometimes my work schedule won't allow
me to participate.  You guys know how it is on 6PM in Engineering on
Friday's sometimes.

ModelSim:

I made a demo from scratch that creates a floating point divider using the
MegaFunction Wizard and then running an example simulation on the latest
Web-version of Quartus II and ModelSim from Altera.  I have e-mailed this
off to Phil - he will take a look at it once he's caught up with the
current bug-crunch he's working on.

Note this is for demo. purposes only just trying to illustrate the flow.  I
e-mailed Phil some brief instructions as well.  I have this running on
PennyLane but it should be easy to retarget as necessary or just to run the
simulator stand-alone.  I have also included some fp multipliers, dividers,
square root funtions and absolute value functions, all floating point, in
the PennyLane build to see how much extra space we have in the FPGA.  Even
with all of this we are using only about 50% of the available space and
still have more than 1/2 of the hardware multipliers available.  So this is
good news if we eventually want to do the SWR calc or anything else for
that matter inside the FPGA.

Anyone that is interested in the stand-alone fp div demo please e-mail me
or maybe I can post on to the Wiki someplace.  Dave - which would you
prefer me to do?

Munin:

Kjell mailed me a board.  Does TAPR have the BOM kitted up yet?  Otherwise
I will get a DigiKey order together for the parts + maybe Mouser and Jameco
- what ever it takes to get the parts as I have told Kjell I will take a
look and do some analysis on the design - plus it'll be nice to have a 100W
RF Amp.

SWR:

I think I mentioned this last week - but I made a build of PowerSWR that
will measure SWR on transmission.  AM/FM seems to work best and I am
getting reasonable results on those - LSB/USB not so much yet.  Note this
is working outside of the existing 'tune' feature.  While I have made some
mods on the FPGA side the version I have sent to Phil should work OK with
the version 1.6 build of the PennyLane FPGA.

I have looked at some of the internal clocking on PennyLane and how the ADC
is driven and have asked Phil to get back to me on a few questions that I
have there.  I will probably put a scope on the ADC CLK this weekend to
verify the ADC CLK is running ~ 3MHz.

I don't think the PowerSDR build that I have sent to Phil is ready for any
type of release or posting - but if anyone really wants to take a look
e-mail me and I will send it to you or post it someplace.

Note you will need to have Alex, Mercury and PennyLane installed w/the SWR
cable between Mercury and PennyLane to run this version of PowerSDR to get
the SWR readings.

Excalibur:
I still haven't finished building my Excalibur kit and hope to have this
complete this weekend. :)

73's,
John
AJ6BC
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