[hpsdr] Angelia and Hermes External Clock problem

[Mike Collins]

Hi Clyde and Helmut,

I have also seen lots of dropouts using the external 10MHz clock input.  
All three of my Hermes drop out at different times averaging maybe 1 
each minute or even more often.  Sometimes use external signal gen 
(synced to same 10MHz GPS) and view Scope display in PowerSDR (DSB with 
offset of maybe 1Hz in freq) for longer capture of dropout.

I have also noted the slow risetime on the Hermes 10Mhz diff pair 
output.  Have done a lot of simulations and changing of resistor values 
with some improvements but still drop outs.  Diff pair good for boosting 
signal level but not good enough for making clean digital clock signal 
to the FPGA.  Get more dropouts with the scope probe attached :))

The current design on the Hermes and Angelia using the diff pair is 
marginal.  The FPGA clock input does not have a schmitt trigger so 
responds to noise on the slow edge.  They don't list a min edge speed in 
the data sheet; but they should.

What the design really needs is a 3V schmitt trigger buffer (following 
the diff pair).  The cleanest thing for me was to make a small "L 
shaped" pcb  (1" X .71") that overlays J20 (pin 2,4 10MHz output, 
input), J23 pin 2 (3.3VD power), and J24 pns 1 &2 (DGND and jumper for 
input connector).  The pcb has DGND on top and 3.3VD on bottom side.  I 
used a 74LVC1G14 single schmitt trigger inverter to buffer the signal.  
Only thing else on the board is a .1uF across the power for the heck of it.

With this little pcb installed over J20,23,24  the 10MHz is now rock 
solid.  Looking at the in vs out on the buffer shows a much faster and 
cleaner signal being sent to the FPGA.  Side by side with a stock Hermes 
the changes is real noticeable

This little pcb was pretty easy to make with just an exacto knife so I 
made 3 of them: one for each Hermes.

I have not seen a single drop out since so think this buffer is 
working.  The 74LVC1G14 was a perfect device for this application.

73,  Mike Collins   KF4BQ


On 6/5/2013 12:35 PM, Clyde Washburn wrote:
>
> My new 100D would wander in and out of lock no matter what 10MHz level 
> was applied externally.  It turns out the problem is the Exteral Clock 
> input PNP diff pair was producing only 0-2V logic output, and with 
> poor risetime, so the slope going thru 1.5V is really slow.  
> Paralleing the 51 ohm emitter resistor with 100 ohms brought the 
> output up to 0-3V, but the risetime, while better is still far slower 
> than the 10MHz clock module, when it is connected.  Now it drops out 
> of lock at -10dBm in, but my concern os that the risetime only 
> improves by 2:1 with drive of +10dBm -- so it's still a marginal 
> condition.  There appears to be substantial capacitive loading on the 
> output clock line, which begs for a totem-pole driver after the diff 
> pait, rather than the 150 ohm resistive source provided by the diff 
> pair.  Who is the keeper of the integrity of the Angelia design?
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/attachments/20130819/57f45836/attachment-0002.htm>