[hpsdr] Angelia External Clock problem

[Helmut, DC6NY]

Hi Clyde,

Sorry I see no other response on your posting and I'm not familiar with
Angelia, but I suppose the circuitry is same as on Hermes. I think you have
chosen the correct 10 MHz select jumper, disconnecting the internal TCXO
from the line. As far as I know from Hermes the 10 MHz signal directly feeds
an I/O port of the FPGA. This means no significant capacitive load.
The common emitter resistor on the Hermes board is 100E and the collector
resistor 270E, that's important to keep the output level below 3.3V. More
will destroy the FPGA port(!).
Usually an external 10 MHz source providing approx. 200 mV sine wave will
work fine.

Again, I have not the schematics of Angelia on hand, my hints refer on
Hermes. But you can check a possible difference quite easily.

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: hpsdr-bounces at lists.openhpsdr.org
[mailto:hpsdr-bounces at lists.openhpsdr.org] Im Auftrag von Clyde Washburn
Gesendet: Mittwoch, 5. Juni 2013 18:35
An: hpsdr at lists.openhpsdr.org
Betreff: [hpsdr] Angelia External Clock problem

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