[hpsdr] Angelia External Clock problem

[Abhi A]

Hello Clyde,

The Angelia EXT clock input circuit is an exact copy of Hermes except that
the collector resistor is lower, this was required as the Cyclone IV device
worked better with a lower impedance, the design works fine with 200mV sine
wave as Helmut has suggested, it is also important to ensure the PP voltage
does not cross 3.3v,

WRT your Rx problem is this a recurring problem? if not I would suggest a
reboot and a PSDR database reset to see if that cures the problem, if not
further investigation would be required,

73s,
Abhi


Who should be notified of Angelia hardware issues?

My new 100D would wander in and out of lock no matter what 10MHz level
was applied externally.  It turns out the problem is the
Exteral Clock input PNP diff pair was producing only 0-2V logic
output, and with poor risetime, so the slope going thru 1.5V is
really slow.  Paralleing the 51 ohm emitter resistor with 100 ohms
brought the output up to 0-3V, but the risetime, while better is
still far slower than the 10MHz clock module, when it is connected.
Now it drops out of lock at -10dBm in, but my concern os that
the risetime only improves by 2:1 with drive of +10dBm - so it's still
a marginal condition.  There appears to be substantial
capacitive loading on the output clock line, which begs for a
totem-pole driver after the diff pait, rather than the 150 ohm
resistive source provided by the diff pair.  Who is the keeper of the
integrity of the Angelia design?

 __________________

Clyde Washburn, K2UE
k2ue at rochester.rr.com
<http://lists.openhpsdr.org/listinfo.cgi/hpsdr-openhpsdr.org>

82 Lasalle Pkwy

Victor, NY 14564-9610

585-317-7006
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