[hpsdr] Angelia External Clock problem

[Helmut, DC6NY]

Hi Clyde,

if things are ok with the internal TCXO, you can be sure that line to the
FPGA is also ok, because this device accepts only a maximum load of 15 pf.
Please check the signal level and wave form at pin 4 (J20, without load, no
jumpers). 
Thanks to Bill  for the schematics, but I guess in the current version R142
is 150E instead of 270E.

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: Clyde Washburn [mailto:k2ue at rochester.rr.com] 
Gesendet: Mittwoch, 5. Juni 2013 20:33
An: 'Helmut, DC6NY'; hpsdr at lists.openhpsdr.org
Betreff: RE: [hpsdr] Angelia External Clock problem

Helmut, all the resistors values are different in Angelia, but the circuit
is the same.  They are actually running at twice the current of Hermes, so
you would think the risetimes would be good, on the other hand it's not
close to the Altera chip, and if the Zo of the trace is low (likely if they
are trying to shield it), you could have the 30 or so pF that would account
for the slow rise.  The on-board standard has fast risetime, but lots of
ringing, suggesting the load is nasty.

__________________
Clyde Washburn, K2UE
k2ue at rochester.rr.com
82 Lasalle Pkwy
Victor, NY 14564-9610
585-317-7006



-----Original Message-----
From: Helmut, DC6NY [mailto:dc6ny at gmx.de]
Sent: Wednesday, June 05, 2013 2:15 PM
To: 'Clyde Washburn'; hpsdr at lists.openhpsdr.org
Subject: AW: [hpsdr] Angelia External Clock problem

Hi Clyde,

Sorry I see no other response on your posting and I'm not familiar with
Angelia, but I suppose the circuitry is same as on Hermes. I think you have
chosen the correct 10 MHz select jumper, disconnecting the internal TCXO
from the line. As far as I know from Hermes the 10 MHz signal directly feeds
an I/O port of the FPGA. This means no significant capacitive load.
The common emitter resistor on the Hermes board is 100E and the collector
resistor 270E, that's important to keep the output level below 3.3V. More
will destroy the FPGA port(!).
Usually an external 10 MHz source providing approx. 200 mV sine wave will
work fine.

Again, I have not the schematics of Angelia on hand, my hints refer on
Hermes. But you can check a possible difference quite easily.

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: hpsdr-bounces at lists.openhpsdr.org
[mailto:hpsdr-bounces at lists.openhpsdr.org] Im Auftrag von Clyde Washburn
Gesendet: Mittwoch, 5. Juni 2013 18:35
An: hpsdr at lists.openhpsdr.org
Betreff: [hpsdr] Angelia External Clock problem

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