[hpsdr] Standalone WSPR beacon

[Phil Harman]

Hi Berndt,

* Date and time is feed as TTL RS232 into an I/O pin on Penny(Lane). This
comes from the TTL RS232 port on the GPS module (Jupiter) I used. The GPS
receiver must NOT be in NMEA mode since the time data can drift with
respect to the 1PPS in this mode.

* Yes, it could exist with the current FPGA code and be selected with an
I/O link on power-up

* Only supports Penny(Lane) but since the hardware is much the same would
be a simple port.  There are a number of I/O pins on Hermes (shared with
DEBUG_LEDS) that could be used to input the 1 PPS and TTL Level date/time
from the GPS receiver.  When using a Jupiter GPS module you get an
accurate 10kHz reference - I also feed that to Penny and phase lock the
122.88MHz clock to it - we could do the same with Hermes.

* Current code is available in two parts 1) the original WSPR code from
KD5TFD and the GPS interface in a 2m Chirp beacon that I wrote.

73 Phil...VK6APH


> G'day Phil,
>
> many thanks for your reply.
>
> Its been a while since using WSPR on Pennylane, but remember the
> transmission slowly sliding outside the transmit window using the
> internal clock. It was the reason why I stopped using it at that time.
> This shouldn't be a problem when using an external timing reference such
> as a GPS.
>
> A few questions:
>
> * How do you feed date and time to Pennylane/Penelope?
> * Could WSPR coexist within the standard firmware?
> * Does the current code base support Hermes?
> * Is source code available?
>
> 73, Berndt
> VK5ABN
>
> On Tue, 2013-03-26 at 09:07 +0800, Phil Harman wrote:
>> Hi Berndt,
>>
>> I did solve that issue by reading the date and time from the GPS
>> receiver.
>> I also built a standalone 2m beacon (VK6RIO) using this technique which
>> I
>> hope will go in service shortly.
>>
>> One item that prevents the code from becoming more useful is that the
>> WSPR
>> data is hard coded into the FPGA. In which case you have to compile the
>> code using Quartus for every callsign etc.
>>
>> A better solution would be to add the WSPR data to the code stored in
>> the
>> EEPROM. We could store the data at a specific address in the EEPROM and
>> merge it with the FPGA data.
>>
>> So the steps would be:
>>
>> 1. Modify the FPGA code to read the WSPR data from EEPROM.
>> 2. Write PC code to generate the required WSPR code (already available),
>> read the .rbf file and merge the files.
>>
>> Nice little 'weekend' project :)
>>
>> Thanks to Bill, KD5TFD, for writing the original WSPR FPGA code.
>>
>> 73 Phil..VK6APH
>>
>>
>>
>>
>> > ***** High Performance Software Defined Radio Discussion List *****
>> >
>> > G'day,
>> >
>> > what has become of the "Standalone WSPR Beacon" project that used the
>> > Penelope/Pennylane? There was some experimental code, but did it ever
>> > make it to a release? From memory, the problem was that it didn't had
>> > synchronisation with an external clock, e.g. time_of_day and 1PPS, and
>> > needed to be started at the beginning of an even 2min period.
>> >
>> > 73, Berndt
>> > VK5ABN
>> >
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>
>
>
>



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