[hpsdr] Clarification question- Hermes & Alex

[dave powis]

Joe, Dick,

Many thanks for the guidance and clarification - it was sort of what I expected, but it wasn't quite what I was reading into the words!

Best 73,
Dave



________________________________
 From: Joe Martin K5SO <k5so at valornet.com>
To: dave powis <g4hup at btinternet.com> 
Cc: "phil at pharman.org" <phil at pharman.org>; HPSDRlist <hpsdr at lists.openhpsdr.org> 
Sent: Sunday, 12 May 2013, 16:54
Subject: Re: [hpsdr] Clarification question- Hermes & Alex
 

Hi Dave, 

To add a bit of additional info to Dick’s response,

Yes, the Alex bus is an SPI bus in the Hermes Verilog code design in the FPGA (not an i2c bus).  Indeed, there are several SPI buses (all independent of each other) in the Hermes Verilog code design that facilitate comm to/from various chips and the Alex connection header J15 on the Hermes board but don’t let that trouble you. The comm protocol and pin/ribbon cable wiring to Alex is described in detail in the the Alex manual.  

From a software/firmware viewpoint, the Alex control signals are passed from the PC program to Hermes via the command and control bytes within the ethernet comm path between PC/Hermes, in accordance with the USB comm protocol document (v1.48) on the SVN.  Hermes then controls the signals on the ribbon cable to Alex to switch the various relays as described in the Alex manual.  

If you need more assistance or wish more detailed information feel free to ask!

73,  Joe K5SO
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