[hpsdr] Fwd: filtering options in FPGA

Mon Sep 23 18:18:16 PDT 2013

Hi John,

Thanks for you post regarding compression options.

I also think the WebSDR receiver by PA3FWM is a great concept and one that
I'm keen to implement in a Hermes or Angelia board.

It should be possible to decimate in the FPGA to give us 0-30MHz of
spectrum that could be fed to an associated PC or SBC via the Gigabit
interface.

Having a WebSDR receiver based on a Hermes or Angelia board located at a
well equipped club/contest station that is otherwise infrequently used
could be of great interest to the club members.

I don't presently have enough spare time to work on this but if anyone is
interested in such a 'weekend project' then I'd be happy to assist.

73 Phil...VK6PH

> ***** High Performance Software Defined Radio Discussion List *****
>
> I am still quite green when it comes to FPGA but I am fairly confident
> that any algorithm able to compress the ~2Gbps of ADC data by 50% will
> require more memory than can be made available on the FPGA. Plus it is
> impossible for a lossless algorithm to make a 50% guarantee anyway.
> Perhaps something could be implemented on Angelia which has 4MB of
> SRAM, but there are far easier alternatives to implementing a
> compression algorithm in Verilog.
>
> I am not familiar enough with the rest of the hardware that may rely
> on the 122.88MHz clock, but the ADC supports running at a lower rate.
> One could lower the clock to around 60MHz in order to sample only
> 0-30MHz and thereby drop the datarate of the raw samples below 1Gbps.
> The wideband WebSDR receiver by PA3FWM at
> http://websdr.ewi.utwente.nl:8901/ uses this approach. From what I
> have read his ADC (LTC2216) runs at 77.76 MHz, so he has to decimate 4
> bits/sample in the FPGA to fit into 1gbps, but it does work very well
> from what I can tell.
>
> The second way would be in some ways more complex since it involves
> designing a new piece of hardware but in some ways simpler since the
> main HPSDR firmware would not have to change much: The FPGA could
> simply relay raw ADC samples to a dedicated LVDS (or similar)
> interface to a dedicated high speed USB3, PCI Express, or 10GBe
> interface dedicated only to sending raw samples to the PC. I think
> this could be done with Angelia and Mercury since they have available
> pins. I don't know about Hermes. One advantage to this approach is
> that the radio could be used normally with existing software to adjust
> BPF, filters, preamp, etc. while the secondary interface would permit
> raw samples to be captured if it were attached. You might think of
> this as the SDR equivalent of a radio's IF interface, and it may
> become useful in the future to have such a thing.
>
> 73, John KF5SAB
>
>
> On Sun, Sep 22, 2013 at 9:20 AM, Ken N9VV <n9vv at wowway.com> wrote:
>>
>> Phil/Ken,
>> I remember how eager N4HY was to see "FLAC" used for a compression
>> algorithm with I/Q signals because it does NOT DISTORT PHASE as
>> do many of the traditional compression algorithms. Perhaps FLAC
>> (OpenSource) would provide a good starting point for 2x to 4x
>> compression(?).
>>
>> Bob, N4HY, was applying FLAC to the gigantic
>> WAV files created by SWL who were recording long sessions of
>> their bandwidth from QSD receivers. It is disappointing to see
>> that FLAC as not caught the attention of that group, where it
>> would reduce the size of their WAV files by 3x to 4x based on
>> my experiments using Audacity against the WAV files :-)
>>
>> wonderful experiments, please keep up the forward looking ideas,
>> all the best Phil for a rapid and full recovery,
>> cheers
>> 73 de Ken N9VV
>>
>> On 9/21/2013 11:11 PM, k3it wrote:
>>>
>>> Hi Phil
>>>
>>> On Sat, Sep 21, 2013 at 11:21 PM, Phil Harman <phil at pharman.org
>>> <mailto:phil at pharman.org>> wrote:
>>>
>>>     I’d estimate about 5 mins work + compile time.
>>>
>>>
>>> Sounds easy, I should be done in about a month then :)
>>>
>>> I think this line needs to be replaced with something that casts 18 bit
>>> samples from CIC to 24 bit out_data_I2/Q2 and may be double the
>>> decimation rate in filter "B"
>>>
>>> firX8R8 fir2 (clock, decimB_avail, decimB_real, decimB_imag,
>>> out_strobe,
>>> out_data_I2, out_data_Q2);
>>>
>>>
>>>     My personal preference is to send raw ADC samples to the PC, or a
>>>     dedicated single board computer (SBC), and do ALL the processing
>>>     there Smile.
>>>
>>>
>>>   I wonder if the FPGA can do real time data compression so that all
>>> data fits into 1 Gbit.  I guess about 3x-4x compression ratio would be
>>> needed at close too 300 MB/s rate.  Or is there a better way?
>>>
>>> Hope you are feeling better!
>>>
>>> 73
>>> Vasiliy
>>>
>>>     *From:* k3it <mailto:gokoyev+k3it at gmail.com>
>>>     *Sent:* Sunday, September 22, 2013 10:32 AM
>>>     *To:* HPSDR list <mailto:hpsdr at lists.openhpsdr.org>
>>>     *Subject:* [hpsdr] filtering options in FPGA
>>>
>>>     ------------------------------------------------------------------------
>>>     Does anybody know how big of an effort would be to modify the
>>>     current Hermes firmware to send the RX streams after the CIC
>>> filters
>>>     and exclude all FIR processing?   I'd like to run an experiment
>>> with
>>>     implementing a decimating FIR filter on the PC.
>>>     For example I'd like CIC decimate to 384k in FPGA and then CFIR
>>>     decimate by 4 on the PC to get 96k finished spectrum.  is there
>>>     anything wrong with this approach?
>>>     I want to do this for two reasons
>>>     - get feet wet with Verilog
>>>     - see how much FPGA space can be recovered by moving part of the
>>>     processing to the PC
>>>     --
>>>     73! Vasiliy K3IT
>>>
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