[hpsdr] [KenSPAM] Draw circuits --> generate VHDL/Verilog

[Ken N9VV (Win-7/64)]

Papilio DesignLab and small SBC:

" It lets you draw up circuits without investing time and energy in 
learning VHDL/Verilog." <LOL>

https://papilio-duo.backerkit.com/hosted_preorders

<URL: 
https://www.kickstarter.com/projects/13588168/papilio-duo-drag-and-drop-fpga-circuit-lab-for-mak?ref=category
 >

dit dit
de N9VV