[hpsdr] FW: SBC Inforce 6410

[Terry Fox]

Hey Graham,
You are correct that the schematics have not been released, which is one concern of mine.  There have been partial diagrams released, but not enough to understand everything involved.  Some people have also taken high resolution pix in order to help reverse engineering, although with a multi-layer board that’s not easy!  I notice that the 1M input impedance spec also shows the higher-voltage input (+/- 20V max).  I wonder if you put it in lower max voltage range (4V IIRC), what that does to the input impedance.  The output impedance of the DAC section is 50 ohms, so no transformation required there.

As far as I know, nobody has modified the RP hardware in any way so far.  There has been an ongoing discussion regarding changing the sample clock oscillator from 125MHz to 122.88MHz to simplify interfacing the audio samples.  I wish that there was a schematic available, as I would also like to remove the low-pass filter, so subsampling could be done with the RP. 

I performed some initial tests a while back, and found that the RP can be VERY SLIGHTLY less sensitive than other SDRs.  Another preamp may be enough to fix that for the most demanding usage.  I think it already has a 6400/6405 or similar buffer in front of the ADC inputs.  It certainly performs similar to other 14-bit SDRs, such as the HiQSDR.  I need to compare it again to my SDR-IQ.  I don’t see 20dB difference by any means, with a good (R&S) signal generator.  The RP has already been used on the air for digital modes on 20M I think.  It probably won’t perform as well as a Hermes or Mercury, but should be at least as good (generally) as the Hermes-Lite.

BTW, the RP seems fine for 1.8MHz and higher, but has some spurs at 474kHz and lots of them at 137kHz.  My testing was with an RP sitting out in the open and their (noisy) wall wart.  Using a clean 5V supply and putting the RP in a metal box would clean that up to a large degree.

It would be nice to perform more serious testing on the RP.  I have some of the test equipment, but lack the time right now.  I have committed to do some transmit testing in the near future – likely after the first of the year.

I still think that for the price, it’s very hard to beat.  Especially with the combined FPGA/ARM fabric of the Zynq chips.  I realize that most people here are in the Altera camp, but I’ve played a little with Xilinx, and with people like Pavel working on it, the learning curve is somewhat less.  Pavel is actively interested in furthering his efforts related to SDR activities, and very open to suggestions and working with others.

73, Terry, N4TLF



From: Graham / KE9H 
Sent: Thursday, December 17, 2015 2:38 PM
To: Terry Fox 
Cc: HPSDR 
Subject: Re: [hpsdr] FW: SBC Inforce 6410

Terry:


The inputs on the standard "Red Pitaya" are oscilloscope probe inputs, and have about 20 dB loss with respect to a properly designed receiver direct input for the data converter. 

Are the groups using the "Red Pitaya" as a receiver modifying the hardware?  

I was not aware that Red Pitaya's manufacturer had released schematics, so it would have to be a reverse engineering effort.


Thanks,

--- Graham / KE9H

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