[hpsdr] CW sidetone through speakers on PC instead of Headphoneon ANAN SDR

[Bryan Rambo]

With VAC RX latency now clipping along at 14ms, it might be time to revisit
it's use with CW sidetone? 

-----Original Message-----
From: Hpsdr [mailto:hpsdr-bounces at lists.openhpsdr.org] On Behalf Of Joe
Martin
Sent: Thursday, May 05, 2016 9:27 AM
To: Scott Traurig
Cc: melm at reliable.net> <melm at reliable.net; hpsdr
Subject: Re: [hpsdr] CW sidetone through speakers on PC instead of
Headphoneon ANAN SDR

***** High Performance Software Defined Radio Discussion List *****

After examining the current USB protocol document (v1.58) and the Orion
Verilog firmware design as a typical example of firmware I see that the
option to use FPGA-generated CW or PC-generated CW is available on the
current protocol as welll as the new protocol.  I thought it was!

In the current protocol the feature switching is accomplished via bit[0] of
C1 from the PC when C0 = 0001_111x.  But in my cursory examination of the
HPSDR PowerSDR menus I don't find an explicit control option in HPSDR
PowerSDR to use use that bit.  It's possibler that I'm not looking in the
right place in HPSDR PowerSDR for the control?  I haven't dug through the
source code for HPSDR PowerSDR to look for the thing there as it's use with
VAC for monitoring CW is impractical anyway.  

Anyway, I thought I'd mention that the switching feature that was mentioned
in this thread is actually provided in the current protocol document and it
is in fact coded and supported in the firmware designs regardless of whether
it happens to be implemented in any user interface controls in the current
HPSDR PowerSDR software or not.  

73, Joe K5SO

On May 4, 2016, at 10:00 PM, Joe Martin wrote:

> ***** High Performance Software Defined Radio Discussion List *****
> 
> Well, Scott, after examining the current HPSDR PowerSDR software I don't
see that option either.  In fact, I'm having difficulty getting the VAC1 to
even work on my machine with the current software/firmware.  I remember
being able to monitor CW via VAC1 in earlier versions but perhaps that is no
longer possible.  I know there has been a lot of work on the VAC code in
HPSDR PowerSDR since I used it in previous versions of HPSDR PowerSDR.  
> 
> The ability to disable internal (to the FPGA) CW generation does exist in
the presently not-released new protocol via the Transmitter-Specific port
command packet protocol (byte 5, bit 1), so I seem to have been confused
about that also being in the current-protocol when I sent my comment.
Confusing new and old protocol features is a hazard of working on both
simultaneously, I apologize for that.  
> 
> As I stated earlier though, and it's still true, VAC is not a viable
option for monitoring CW with HPSDR PowerSDR due to the inherent latency of
the VAC paths.  
> 
> 73, Joe K5SO
> 
> 
> On May 4, 2016, at 8:22 PM, Scott Traurig wrote:
> 
>> Where is that option in the setup, BTW?
>> 
>> 73,
>> 
>> Scott
>> 
>> On Wed, May 4, 2016 at 10:12 PM, Joe Martin <k5so at k5so.com> wrote:
>> It can be done if you disable FPGA CW generation (i.e., select the option
to generate the CW in the PC rather than in the FPGA) but as a practical
matter it's a moot point due to the latency involved with VAC.
>> 
>> 73, Joe K5SO
> 
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