[hpsdr] 12bit vs 16bit ADC (Was Re: Hpsdr Digest, Vol 141, Issue 5)

[Steve Haynal]

Hi Ben,

I agree that much of the work done by HPSDR is top quality. I am very
grateful to the FPGA firmware authors and schematic engineers for sharing
their work. Also, I understand your need for the best possible measurements
given your research. I found several very interesting hits on the net for
your research, including this one
<http://www.arrl.org/news/nvis-research-paper-available>.

I would like to hear more use cases where a 16 bit ADC is clearly
advantageous over a 12 bit ADC. It is my opinion that for most typical use,
a 12 bit ADC is just fine. I've been working on and using Hermes-Lites for
years now, and I've had access to a Hermes in the past, and have seen
little difference.

In terms of dynamic range, at my QTH in Portlandia, I do not see ADC
clipping when running with a full size 40M antenna. This is with the LNA
gain set to adequate levels (+12 dB to + 20dB) and the antenna connected
without preselection filtering.

I often use a ZM-2 <https://steadynet.com/emtech/> Z-match tuner which does
provide some preselection. With this in place, I can increase the LNA gain
to +36dB (far beyond the point of better returns) before I see ADC
clipping. This means that even the ZM-2 preselection is giving me another
16 to 20dB of dynamic headroom, or 2 to 3 bits. As expected, preselection
does provide more dynamic headroom when and if needed.

Where is the noise that preselection filters out really coming from? Are
preselectors for every band required? Jim N2ADR (author of Quisk, creator
of HiQSDR predecessor) made an interesting experiment where he adds just a
single HPF at ~3MHz to his Hermes-Lite. He found that just this single
filter provides very similar results to preselection in terms of dynamic
range extension. Because of this, we are adding a single switchable HPF to
the Hermes-Lite 2 filter board. Jim also added bandscope and an ADC usage
indicator to Quisk.

With regards to the current SDR landscape, many new offerings are going
with 12-bit. Consider the ASIC used in limesdr, or the new RFSOC
<https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html> from
Xilinx. These also run at a higher sampling rate so do benefit from
processing gains.

With regards to cost, one must pay a pretty penny more for equivalent
16-bit when compared to 12-bit, so there better be clear advantages. For
example, we can build the Hermes-Lite 2 in small quantities in China for
under $200 per unit. This includes the 5W PA. (All design files, including
fabrication bids, are posted on the github site.) My research of higher bit
ADCs indicates I could never come near that cost in small quantities.

And if one is willing to do diversity, are 4 12-bit units better than 1
16-bit unit for the same cost? If I remember correctly, one gains 3dB
dynamic range (not 6dB as might be thought as noise increases too) for each
doubling of the number of synchronized receivers. This does not factor in
directional gains. This brings the effective number of bits of 4 12-bit
ADCs (~11) much closer to the ENOB of a single 16-bit ADC (~13).

Clock phase noise is less restrictive and hence less expensive for 12-bit
too, assuming comparable sampling frequencies.

There are other considerations than just dynamic range and price. For
example, other types of distortion and nonlinearities in the ADC and
front-end, some of which are independent of the number of bits. But again,
I'd like to know how often these differences matter in practice.

I'd like to know when and how often a 16-bit unit has led to a contact that
would have been missed with a 12-bit unit, or even when a 16-bit unit led
to a better operating experience over a 12-bit unit. I'm not looking for
lab measurements, but actual qualitative use experiences, as that is what
counts most in my mind. I don't care if my car can do 200 miles per hour if
the highest speed limits in my driving range are 70 miles per hour...

There are people of this list with access to both 14-bit and 16-bit HPSDR
units, and maybe even some 12-bit units. What differences have you seen in
practice?

73,

Steve
KF7O







>
> Message: 2
> Date: Tue, 07 Nov 2017 18:44:20 +0100
> From: pa5bw <pa5bw at xs4all.nl>
> To: hpsdr at lists.openhpsdr.org
> Subject: Re: [hpsdr] Hpsdr Digest, Vol 141, Issue 3
> Message-ID: <79dxq144w100ydyyk9pi65e9.1510075737105 at email.android.com>
> Content-Type: text/plain; charset="utf-8"
>
> Hi Steve,
> For my application I would not go for a 12-bit receiver. I am.extremely
> happy with the HPSDR. With its 16-bit ADC, well designed input circuitry
> and excellent processing in the FPGA, I can connect a full-size 7 KHz
> dipole without bandfilter without any perceivable IMD. That makes
> scientific experiments so.much easier...
> 73, Ben M/PE5B
>
> Date: Mon, 6 Nov 2017 21:39:26 -0800
> From: Steve Haynal
>
> Hi Ben,
>
> Can you share more details regarding your 8 ADC HPSDR ideas? This is a
> topic that has interested me since I once connected several synchronized
> softrock radios, created several audio streams each "beamed" differently,
> and then decoded all simultaneously with WSPR. The WSPR signal strengths
> could then tell me from which general direction the signal arrived.
>
> One option I've dreamed of is to repurpose an ultrasound IC such as these
> from Analog devices
> http://www.analog.com/en/products/application-specific/
> medical/ultrasound.html
> as a synchronized 8 ADC HF DDC SDR. TI and others also make similar
> ultrasound ICs. These also have built in LNA. Another option is to
> repurpose CCD/Camera/Scanner ICs such as this
> http://www.analog.com/en/products/audio-video/
> cameracamcorder-analog-front-ends/addi7004.html.
> It should be possible to pair one of these ICs with a snickerdoodle (
> http://krtkl.com/) or Z-turn (http://www.myirtech.com/list.asp?id=502) for
> an inexpensive and quick >2 ADC receiver.
>
> We are planning for more than 2 synchronized ADCs and DACs with the
> Hermes-Lite. See www.hermeslite.com. Each Hermes-Lite 2 unit has a single
> ADC and DAC, but we have the ability to synchronize units. One unit is
> designated the master and provides a clock to the second "slave" unit. The
> slave can pass this clock to other slaves in a daisy-chained fashion. Data
> packets from each radio are time stamped and then combined appropriately on
> the host computer.
>
> We also have allocated LVDS pairs for radio to radio communication. This is
> an alternate way to synchronize data.
>
> We plan to do synchronized TX also as each Hermes-Lite unit has a 5W PA.
>
> All of this is designed into the hardware so far. Firmware and software
> development will start early next year. We have ~12 Hermes-Lite 2 units in
> the wild (many more Hermes-Lite 1 units). We are close to finalizing the
> hardware and organizing larger group buys.
>
> The Hermes-Lite 2 is entirely open source and open hardware, without any
> gray areas. You can find all files on github:
> https://github.com/softerhardware/Hermes-Lite2 The entire design was done
> with an open source tool chain as much as possible.
>
> To your original question, you can find schematics for the Angelia at:
>
> https://apache-labs.com/downloadsfiles/1011_ANGELIA_PRODUCTION.pdf
>
> 73,
>
> Steve
> KF7O
>
>
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